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Freescale Semiconductor /MKV43F15 /SIM /MISCTRL2

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Interpret as MISCTRL2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SYNCXBARAPITTRIG0 0 (0)SYNCXBARAPITTRIG1 0 (0)SYNCXBARAPITTRIG2 0 (0)SYNCXBARAPITTRIG3 0 (0)SYNCXBARBPITTRIG0 0 (0)SYNCXBARBPITTRIG1 0 (0)SYNCDACHWTRIG 0 (0)SYNCEWMIN 0 (0)SYNCCMP0SAMPLEWIN 0 (0)SYNCCMP1SAMPLEWIN 0 (0)SYNCCMP2SAMPLEWIN 0 (0)SYNCCMP3SAMPLEWIN

SYNCXBARBPITTRIG0=0, SYNCXBARAPITTRIG0=0, SYNCCMP2SAMPLEWIN=0, SYNCEWMIN=0, SYNCCMP0SAMPLEWIN=0, SYNCDACHWTRIG=0, SYNCXBARAPITTRIG2=0, SYNCCMP1SAMPLEWIN=0, SYNCCMP3SAMPLEWIN=0, SYNCXBARBPITTRIG1=0, SYNCXBARAPITTRIG3=0, SYNCXBARAPITTRIG1=0

Description

Miscellaneous Control Register 2

Fields

SYNCXBARAPITTRIG0

Synchronize XBARA’s Input PIT Trigger 0 with fast clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.
SYNCXBARAPITTRIG1

Synchronize XBARA’s Input PIT Trigger 1 with fast clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.
SYNCXBARAPITTRIG2

Synchronize XBARA’s Input PIT Trigger 2 with fast clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.
SYNCXBARAPITTRIG3

Synchronize XBARA’s Input PIT Trigger 3 with fast clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.
SYNCXBARBPITTRIG0

Synchronize XBARB’s Input PIT Trigger 0 with fast clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.
SYNCXBARBPITTRIG1

Synchronize XBARB’s Input PIT Trigger 1 with fast clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.
SYNCDACHWTRIG

Synchronize XBARA’s output for DAC Hardware Trigger with flash/slow clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.
SYNCEWMIN

Synchronize XBARA’s output for EWM’s ewm_in with flash/slow clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.
SYNCCMP0SAMPLEWIN

Synchronize XBARA’s output for CMP0’s Sample/Window Input with flash/slow clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.
SYNCCMP1SAMPLEWIN

Synchronize XBARA’s output for CMP1’s Sample/Window Input with flash/slow clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.
SYNCCMP2SAMPLEWIN

Synchronize XBARA’s output for CMP2’s Sample/Window Input with flash/slow clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.
SYNCCMP3SAMPLEWIN

Synchronize XBARA’s output for CMP3’s Sample/Window Input with flash/slow clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data